CMOS Implementation of Programmable Logic Gates and Pipelined Full Adders using Threshold Logic Gates Based on NDR Devices
dc.contributor.author | Salem, Nema | |
dc.contributor.author | ElSayed, Mohamed | |
dc.contributor.author | Mira, Ramy | |
dc.date.accessioned | 2023-03-16T04:32:08Z | |
dc.date.available | 2023-03-16T04:32:08Z | |
dc.date.issued | 2004-08-16 | |
dc.identifier.citation | 5 | en_US |
dc.identifier.doi | 10.1109/NRSC.2004.239887 | en_US |
dc.identifier.uri | http://hdl.handle.net/20.500.14131/681 | |
dc.description.abstract | This paper presents a new prototyping technique, which allows efficient verification of circuit concepts based on negative differential resistance (NDR) devices. This prototype, which is called MOS-NDR, has been used to implement programmable logic gates and pipelined-ripple-carry full adders using linear threshold gates (LTGs). | en_US |
dc.publisher | IEEE | en_US |
dc.subject | CMOS logic circuits , Logic gates , Logic devices , Programmable logic arrays , Programmable logic devices , Adders , Resonant tunneling devices , Logic circuits , Prototypes , CMOS technology | en_US |
dc.title | CMOS Implementation of Programmable Logic Gates and Pipelined Full Adders using Threshold Logic Gates Based on NDR Devices | en_US |
dc.contributor.researcher | External Collaboration | en_US |
dc.subject.KSA | NS | en_US |
dc.source.index | Scopus | en_US |
dc.contributor.department | Electrical and Computer Engineering | en_US |
dc.contributor.firstauthor | Mira, Ramy | |
dc.conference.location | Cairo, Egypt | en_US |
dc.conference.name | 21 national radio science conference NRSC2004 | en_US |
dc.conference.date | 2004-03-16 |