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dc.contributor.authorSalem, Nema
dc.contributor.authorElSayed, Mohamed
dc.contributor.authorMira, Ramy
dc.date.accessioned2023-03-16T04:32:08Z
dc.date.available2023-03-16T04:32:08Z
dc.date.issued2004-08-16
dc.identifier.citation5en_US
dc.identifier.doi10.1109/NRSC.2004.239887en_US
dc.identifier.urihttp://hdl.handle.net/20.500.14131/681
dc.description.abstractThis paper presents a new prototyping technique, which allows efficient verification of circuit concepts based on negative differential resistance (NDR) devices. This prototype, which is called MOS-NDR, has been used to implement programmable logic gates and pipelined-ripple-carry full adders using linear threshold gates (LTGs).en_US
dc.publisherIEEEen_US
dc.subjectCMOS logic circuits , Logic gates , Logic devices , Programmable logic arrays , Programmable logic devices , Adders , Resonant tunneling devices , Logic circuits , Prototypes , CMOS technologyen_US
dc.titleCMOS Implementation of Programmable Logic Gates and Pipelined Full Adders using Threshold Logic Gates Based on NDR Devicesen_US
dc.contributor.researcherExternal Collaborationen_US
dc.subject.KSANSen_US
dc.source.indexScopusen_US
dc.contributor.departmentElectrical and Computer Engineeringen_US
dc.contributor.firstauthorMira, Ramy
dc.conference.locationCairo, Egypten_US
dc.conference.name21 national radio science conference NRSC2004en_US
dc.conference.date2004-03-16


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