CMOS Implementation of Programmable Logic Gates and Pipelined Full Adders using Threshold Logic Gates Based on NDR Devices

Abstract

This paper presents a new prototyping technique, which allows efficient verification of circuit concepts based on negative differential resistance (NDR) devices. This prototype, which is called MOS-NDR, has been used to implement programmable logic gates and pipelined-ripple-carry full adders using linear threshold gates (LTGs).