Development and Implementation of pipeline Convolutional Coding using FPGA
Abstract
Channel coding is essential for ensuring reliable data transmission in challenging wireless communications. Improving spectrum efficiency involves leveraging efficient forward error correction (FEC) methods. Viterbi decoding plays a critical role in Convolutional channel coding for accurate error detection and correction, particularly in LTE and Satellite communication systems. This article discusses the simulation and FPGA implementation of a newly proposed non-systematic Convolutional system featuring a block interleaver and 64-QAM Mapping under AWGN and Rayleigh channel conditions. The system adopts a Convolutional coding rate of 1/3 and a constraint length of 7, utilizing a Trellis diagram for encoding and the Viterbi algorithm for decoding with hard decision decoding. Additionally, a pipeline coding approach is employed. Simulations are conducted using MATLAB-R2023b, and the implementation is executed on Virtex 6 (XC6VLX240T) FPGA using Xilinx 14.7. The study reveals that the pipeline technique demands more FPGA resources compared to traditional methods while still utilizing a small resource block from Virtex 6, with 3% and 9% usage of slice registers and LUTs, respectively. Moreover, the system's timing is reduced from 24 to 14 clock cycles, enhancing the efficiency of entirely LUT-FF pairs from 55% to 63%.Department
Electrical and Computer EngineeringPublisher
Minia University, Faculty of EngineeringJournal title
Journal of Advanced Engineering Trendsae974a485f413a2113503eed53cd6c53
https://doi.org/10.21608/jaet.2024.294711.1290