Energy-efficient architecture for high-performance FIR adaptive filter using hybridizing CSDTCSE-CRABRA based distributed arithmetic design: Noise removal application in IoT-based WSN
Mohammed, Abdul Majid, Raghavendra, D. Kulkarni
Mohammed, Abdul Majid,
Raghavendra, D. Kulkarni
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Date
2024-07-01
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Abstract
An energy-efficient architecture of high-performance FIR adaptive filter design using approximate distributed arithmetic (DA), which is integrated with canonic signed digit-based triangular common sub expression elimination (CSDTCSE) and carry-resist adder based Booth recorder adder (CRABRA) is proposed for noise removal in sensor nodes. Distributed arithmetic is coupled with two signed 32-bit, 16-bit radix-8 Booth algorithms and approximate computation under 2-bit adder to design FIR adaptive filter for decreasing partial products (PP) together with accumulation circuits. The truncation of LSB in the PP is presented to approximate the PP to reduce memory complexity and hardware overhead. An approximation recoding adder decreases the energy usage, area, and critical path. Approximate Wallace trees are applied to the PP accumulation to lessen the latency. The canonic signed digit-based triangular common sub-expressions elimination framework is proposed, which significantly reduces a count of logic operators and logic depth in implementing the FIR filter. The proposed algorithm is activated in Verilog coding and synthesized using Xilinx 14.5 ISE simulation software. The proposed design successfully reduces delay, area, and power by maintaining better accuracy with performance.