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CMOS Implementation of Programmable Logic Gates and Pipelined Full Adders using Threshold Logic Gates Based on NDR Devices

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ElSayed, Mohamed
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Mira, Ramy
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Supervisor
Subject
CMOS logic circuits , Logic gates , Logic devices , Programmable logic arrays , Programmable logic devices , Adders , Resonant tunneling devices , Logic circuits , Prototypes , CMOS technology
Date
2004-08-16
Collections
ECE - Conference Papers
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Ramy Mira D03.doc
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Abstract
This paper presents a new prototyping technique, which allows efficient verification of circuit concepts based on negative differential resistance (NDR) devices. This prototype, which is called MOS-NDR, has been used to implement programmable logic gates and pipelined-ripple-carry full adders using linear threshold gates (LTGs).
Department
Electrical and Computer Engineering
Publisher
IEEE
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Open Access
http://hdl.handle.net/20.500.14131/681
DOI
10.1109/NRSC.2004.239887
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